Virtual function void write (apb_pkt data) Step3: Define action to be taken when a packet is received via the declared analysis port Define the action to be taken when data is received from the analysis port Instantiate the analysis port, because afterall, its a class objectįunction void build_phase (uvm_phase phase) ģ. Uvm_analysis_imp #(apb_pkt, my_scoreboard) ap_imp Step2: Declare and create a TLM Analysis Port to receive data objects from other TB components Add necessary TLM exports to receive transactions from other components and instantiat them in build_phase This is standard code for all componentsįunction new (string name = "my_scoreboard", uvm_component parent = null) Ģ. my_scoreboard is user-given name for this class that has been derived from "uvm_scoreboard"Ĭlass my_scoreboard extends uvm_scoreboard Create a custom class inherited from uvm_scoreboard, register with factory and call function new It is recommended to inherit from uvm_scoreboard than uvm_component so that any additions to uvm_scoreboard class in a future release of UVM will automatically be included in the custom UVM scoreboard when you switch to the newer version. The final task is to compare expected results with the actual output data from DUT. The reference model is also called a predictor and would mimic the functionality of the design. What is a reference model ?Īfter receiving data objects, it can either perform calculations and predict the expected value or send it to a reference model to get expected values. Now the scoreboard can compare between the expected and actual values to see if they match. After that, the same register is read back from the design and the data is actual value which is sent to UVM scoreboard. When a write operation is performed to the design, the scoreboard receives this packet and is the expected value. It usually receives transaction level objects captured from the interfaces of a DUT via TLM Analysis Ports.įor example, write and read values from a RW register should match.
UVM scoreboard is a verification component that contains checkers and verifies the functionality of a design.
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